1. Field of the Invention
The present invention relates in general to integrated circuit devices, and in particular to a method of fabricating an embedded gate electrode for solving the problem of making the tradeoff between junction depth and silicide thickness.
2. Description of the Prior Art
In process for fabricating semiconductor components, as the features of VLSI circuits continue to shrink to 0.5 .mu.m and below, the necessity of decreasing the resistance and capacitance (RC) associated with interconnection paths becomes even more pressing. This is particularly true for MOS devices, in which the RC delay due to the interconnect paths can exceed the delays due to gate switching. The higher the value of the interconnect R (resistance).times.C (capacitance) product, the more likely is the circuit operating speed to be limited by this delay. The conclusion is that low resistivity interconnection paths are critical in order to fabricate dense, high performance devices.
There are several potential approaches to reduce the resistivity of the interconnect to less than 10-15 .OMEGA./sq exhibited by polysilicon. The most widespread approach used in the IC industry is the fabricating application of self-aligned silicide (salicide). Salicide processes are commonly employed to provide a metal silicide layer over the polysilicon gate electrode and over the source/drain regions of the silicon substrate, to facilitate electrically and metallurgically connecting the silicon to metal interconnects. A salicide process normally comprises the following steps. Firstly, a MOS transistor having a gate, source/drain regions, and spacers are formed above a silicon substrate. Secondly, a metallic layer with a thickness of about 200 angstroms to 1000 angstroms is then deposited on the surface of the silicon substrate through a magnetron DC sputtering method. Thirdly, upon application of a high temperature, part of the metallic layer reacts with silicon above the source/drain regions and polysilicon above the gate of the MOS transistor, thereby forming silicide layers. Finally, unreacted residual metal remaining after the reactive process is then removed by a wet etching method, thereby leaving behind the metal silicide layer on the top surfaces of the MOS terminals. Most commonly used materials for the salicide processes are titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt), tungsten (W), molybdenum (Mo), and copper (Cu).
Since the silicide formation consumes part of the source/drain regions, the source/drain regions must be deep enough to prevent spiking of the silicide through the diode junctions, since this would cause junction leakage and lower transistor performance. Deeper junctions in turn also lead to lower transistor performance due to parasitic capacitance and inhibited scalability of the gate length. Thus, a tradeoff must normally be made between junction depth and silicide thickness, since shallower junctions are incompatible with thicker silicide layers.
Heretofore, attempts to form shallow junctions with a thick silicide cover have been less than satisfactory. One such method is referred to as ion-implantation through metal (ITM). In ITM, a metal layer is applied to the silicon surface which will be subsequently doped. Ion-implantation is then conducted through the metal and into the silicon to form the doped region. Silicide is then formed over the doped region by a standard annealing process such as a furnace anneal or a rapid thermal anneal. Unfortunately, to meet the dual objectives of a shallow junction and a thick silicide layer, metal must be deposited to a typical thickness of at least 1,000 Angstroms. Implanting a dopant through a metal layer of 1,000 Angstroms requires high implant energy which can damage the surface of the metal layer and create defects (spiking) by driving some of the metal atoms into the silicon substrate.
An alternative to ITM is to apply a metal layer to the silicon surface which is to be doped and subsequently to implant dopants into the metal rather than through the metal. However, the use of a thick metal layer to meet the objective of a low resistivity silicide layer still requires high implant energy at which to implant dopants.
The above problems need to be addressed if integrated circuits with improved electrical performance and reliable manufacturing processes are to be achieved. Therefore, alternate techniques for solving the problem of making the tradeoff between junction depth and silicide thickness are desired. Thus, a method of fabricating embedded gate electrodes in avoiding junction leakage is introduced into shallow junction processes by the present invention.